1. Field of the Invention
The present invention relates to a method for manufacturing a display device. Specifically, the present invention relates to a method for manufacturing a display device including a wiring formation step by an ink jetting method and a contact plug formation step to electrically connect the wirings.
2. Description of the Related Art
A thin film transistor (TFT) formed by using a thin film on an insulating surface is widely applied to integrated circuits and the like, in many cases, is used as a switching element. Application of a display panel using TFTs greatly expands, in particular, into a large-scale display device. Thus, high definition, high aperture ratio, high-reliability, and growth in size for a screen are required extremely.
A method for manufacturing wirings in such a device using thin film transistors is as follows: after a contact hole to connect to a particular region of a substrate is formed by a combination of photolithography and anisotropic etching, a film of a conductive layer is formed over the entire surface, and then, photolithography and anisotropic etching are preformed by using a mask. (Reference 1: Japanese Patent Laid-Open No. 2002-359246)
As in the above reference 1, in the case where contact holes connecting with a base conductive layer are opened, a resist is patterned by photolithography once, the contact holes are opened selectively by anisotropic etching, and an unnecessary resist is removed. Thereafter, in the case of forming wirings, a conductive layer is deposited over the entire surface, and a resist is patterned by photolithography again, and then, the wirings are processed by anisotropic etching. Like this, two photolithography steps are required for forming up the wirings from the contact holes, and thus, the number of steps is increased. Further, in the case of such a wiring etching treatment, for example, when an ICP etching apparatus is used, selective ratio of a resist and a conductive layer vary and the length or width of the conductive layer varies in the substrate, according to etching conditions such as bias power density, ICP power density, pressure, total flow of etching gases, an oxygenation factor and a temperature of a lower electrode. When an etching treatment is performed, the throughput gets worse since a step of forming a mask is necessary. The conductive layer is formed over the entire surface, and then, an etching treatment is performed to provide the conductive layer with a desired shape, therefore, an unnecessary material is produced. Such a problem is serious in the case of forming wirings over a large size substrate of which side exceeds 1.0 m.